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LOW POWER 2V CMOS SRAM 1 MEG (128K x 8-BIT)
Integrated Device Technology, Inc.
ADVANCE INFORMATION IDT71T024
FEATURES:
* * * * * * * 128K x 8 Organization Wide Operating Voltage Range: 1.8V to 2.7V Speed Grades: 150ns, 200ns Low Operating Power: 11mA (max) Low Standby Power: 5A (max) Low-Voltage Data Retention: 1.5V (min) Available in 32-pin, 13.4mm x 8mm Type I TSOP package
DESCRIPTION:
The IDT71T024 is a 1,048,576-bit very low-power Static RAM organized as 128K x 8. It is fabricated using IDT's highreliability CMOS technology. This state-of-the-art technology, combined with innovative circuit design techniques, provides a cost-effective solution for low-power memory needs. It uses a 6-transistor memory cell. Operation is from a single extended-range 2.5V supply. This extended supply range makes the device ideally suited for unregulated battery-powered applications. Fully static asynchronous circuitry is used, requiring no clocks or refresh for operation. The IDT71T024 is packaged in a JEDEC standard 32-pin TSOP Type I.
FUNCTIONAL BLOCK DIAGRAM
A0
* * *
A16
ADDRESS DECODER
* * *
1,048,576-BIT MEMORY ARRAY
I/O0 - I/O7
*
8
8
I/O CONTROL
8
WE OE CS1
CS2
CONTROL LOGIC
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The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES
(c)1997 Integrated Device Technology, Inc.
MAY 1997
DSC-3779/1
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IDT71T024 LOW POWER 2V CMOS STATIC RAM 1 MEG (128K x 8-BIT)
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
A11 A9 A8 A13
WE
CS2 A15 VDD NC A16 A14 A12 A7 A6 A5 A4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
TSOP (I)
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
OE
A10
CS1
I/O7 I/O6 I/O5 I/O4 I/O3 VSS I/O2 I/O1 I/O0 A0 A1 A2 A3
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TSOP TOP VIEW
TRUTH TABLE(1)
CS1
H X L L L CS2 X L H H H
PIN DESCRIPTIONS
WE
X X H L H I/O0-I/O7 High-Z High-Z DATAOUT DATAIN High-Z Function Deselected - Standby Deselected - Standby Read Write Outputs Disabled
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OE
X X L X H
A0 - A16
Address Inputs Chip Select Chip Select Write Enable Output Enable Data Input/Output Power Ground
Input Input Input Input Input I/O Pwr Gnd
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CS1
CS2
WE OE
I/O0 - I/O7 VDD VSS
NOTE: 1.H = VIH, L = VIL, X = Don't care.
CAPACITANCE
(TA = +25C, f = 1.0MHz)
Symbol CIN CI/O Parameter(1) Input Capacitance I/O Capacitance Conditions VIN = 1dV VOUT = 1dV Max. 6 7 Unit pF pF
NOTE: 3779 tbl 06 1. This parameter is guaranteed by device characterization, but not production tested.
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IDT71T024 LOW POWER 2V CMOS STATIC RAM 1 MEG (128K x 8-BIT)
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM(2) VTERM(3) TBIAS TSTG PT IOUT Rating Terminal Voltage with Respect to VSS Terminal Voltage with Respect to VSS Temperature Under Bias Storage Temperature Power Dissipation DC Output Current Com'l. and Ind'l. -0.5 to +3.6 -0.5 to VDD+0.5V -55 to +125 -55 to +125 1.0 20 Unit V V C C W mA
RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE
Grade Commercial Industrial Temperature 0C to +70C -40C to +85C VSS 0V 0V VDD 1.8V to 2.7V 1.8V to 2.7V
3779 tbl 04
RECOMMENDED DC OPERATING CONDITIONS
Symbol VDD VSS VIH VIL Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Min. 1.8 0 VDD x 0.7 -0.3
(2)
NOTES: 3779 tbl 03 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VDD terminals only. 3. Input, Output,and I/O terminals; 3.6V maximum.
Max. 2.7 0 VDD + 0.3(1) VDD x 0.3
Unit V V V V
NOTE: 3779 tbl 05 1. VIH (max.) = VDD + 1.5V for pulse width less than 5ns, once per cycle. 2. VIL (min.) = -1.5V for pulse width less than 5ns, once per cycle.
DC ELECTRICAL CHARACTERISTICS
VDD = 1.8V to 2.7V, Commercial and Industrial Temperature Ranges
Symbol |ILI| |ILO| VOH VOL Parameter Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Test Conditions VDD = Max., VIN = VSS to VDD VDD = Max., CS = VIH, VOUT = VSS to VDD VDD = 1.8 to 2.7V VDD = 2.3 to 2.7V VDD = 1.8 to 2.7V VDD = 2.3 to 2.7V IOH = -0.3mA IOH = -2mA IOL = 0.3mA IOL = 2mA Min. -- -- VDD - 0.2 1.7 -- -- Max. 1 1 -- -- 0.2 0.4
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Unit A A V V
DC ELECTRICAL CHARACTERISTICS(1, 2)
VDD = 1.8 to 2.7V, VLC = 0.2V, VHC = VDD-0.2V, Commercial and Industrial Temperature Ranges
Symbol ICC2 Parameter Dynamic Operating Current Test Conditions Typ.(5) -70 ns -100 ns -- -- -- -40 to 85C 0 to 70C 40C 25C
NOTES: 1. All values are maximum guaranteed values. 2. Input low and high voltage levels are 0.2V and VDD-0.2V respectively for all tests. 3. fMAX = 1/tRC (all address inputs are cycling at fMAX). 4. f = 0 means no address input lines are changing . 5. Typical conditions are VDD = 2.0V and specified temperature.
Max. 11 9 4 10 5 2 1
Unit mA
CS1 = VLC, CS2 = VHC, Outputs Open,
VDD = 2.7V, f = fMAX
(3)
ICC ISB1
Static Operating Current Standby Supply Current
CS1 = VLC, CS2 = VHC, Outputs Open, WE = VHC, VDD = 2.7V, f = 0(4) CS1 and CS2 = VHC, or CS2 = VLC,
Outputs Open, VDD = 2.7V
mA A
-- -- -- --
3778 tbl 08
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IDT71T024 LOW POWER 2V CMOS STATIC RAM 1 MEG (128K x 8-BIT)
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES
(VLC = 0.2V, VHC = VDD - 0.2V)
Symbol VDR ICCDR tCDR(3) tR(3) Parameter VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time Test Condition -- 1) CS1 VHC and CS2 VHC or 2) CS2 VLC Min. 1.5 -- 0 tRC(2) Typ. (1) -- <1 -- -- Max. -- 5 -- -- Unit V A ns ns
3779 tbl 09
NOTES: 1. TA = +25C. 2. tRC = Read Cycle Time. 3. This parameter is guaranteed by device characterization, but is not production tested.
LOW VDD DATA RETENTION WAVEFORM
DATA RETENTION MODE VDD tCDR 1.8V VDR 1.5V VIH VIH
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1.8V tR
CS
VDR
AC TEST CONDITIONS
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels AC Test Load GND to VDD 3ns VDD x 0.5 VDD x 0.5 See Figure 1
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AC TEST LOAD
VDD 3070 DATAOUT 50pF* 3150
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*Including jig and scope capacitance.
Figure 1. AC Test Load
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IDT71T024 LOW POWER 2V CMOS STATIC RAM 1 MEG (128K x 8-BIT)
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS (VDD = 1.8 to 2.7V, All Temperature Ranges)
71T024L150 Symbol Read Cycle tRC tAA tACS tCLZ tOE tOLZ tOH Write Cycle tWC tAW tCW tAS tWR tWP tDW tDH tOW(1) tWHZ
(1) (1) (1)
71T024L200 Min. 200 -- -- 20 -- -- 20 -- 15 200 160 160 0 0 140 80 0 5 -- Max. -- 200 200 -- 40 100 -- 40 -- -- -- -- -- -- -- -- -- -- 50 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
3779 tbl 11
Parameter Read Cycle Time Address Access Time Chip Select Access Time Chip Select Low to Output in Low-Z Chip Select High to Output in High-Z Output Enable Low to Output Valid Output Enable Low to Output in Low-Z Output Enable High to Output in High-Z Output Hold from Address Change Write Cycle Time Address Valid to End of Write Chip Select Low to End of Write Address Set-up Time Address Hold from End of Write Write Pulse Width Data Valid to End of Write Data Hold Time Write Enable High to Output in Low-Z Write Enable Low to Output in High-Z
Min. 150 -- -- 20 -- -- 20 -- 15 150 120 120 0 0 100 60 0 5 --
Max. -- 150 150 -- 30 75 -- 30 -- -- -- -- -- -- -- -- -- -- 40
tCHZ(1)
tOHZ(1)
NOTE: 1. This parameter is guaranteed by device characterization, but is not production tested.
5
IDT71T024 LOW POWER 2V CMOS STATIC RAM 1 MEG (128K x 8-BIT)
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO. 1(1)
t RC ADDRESS t AA
OE
t OE
CS1
t OLZ
(5)
CS2 t ACS (3) t CLZ (5) DATA OUT HIGH IMPEDANCE t OHZ (5) t CHZ (5) DATA OUT VALID
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TIMING WAVEFORM OF READ CYCLE NO. 2(1, 2, 4)
tRC ADDRESS tAA tOH DATAOUT PREVIOUS DATAOUT VALID tOH DATAOUT VALID
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NOTES: 1. WE is HIGH for Read Cycle. 2. Device is continuously selected; CS1 is LOW and CS2 is HIGH. 3. Address must be valid prior to or coincident with the later of CS1 transition LOW and CS2 transition HIGH; otherwise tAA is the limiting parameter. 4. OE is LOW. 5. Transition is measured 200mV from steady state.
6
IDT71T024 LOW POWER 2V CMOS STATIC RAM 1 MEG (128K x 8-BIT)
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED TIMING)(1, 2, 5) WE
tWC ADDRESS tAW
CS1
CS2 tAS
tCW
tWP (7)
tWR
(3)
WE
tWHZ DATAOUT
(4) (6)
tOW HIGH IMPEDANCE tDW tDH
(6)
tCHZ (6)
(4)
DATAIN
DATAIN VALID
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TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CS1 AND CS2 CONTROLLED TIMING)(1,2,5) CS1
tWC ADDRESS tAW
CS1
CS2 tAS tCW tWR
(3)
WE
tDW DATAIN DATAIN VALID
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tDH
NOTES: 1. WE or CS1 must be HIGH, or CS2 must be LOW during all address transitions. 2. A write occurs during the overlap of a LOW CS1, HIGH CS2, and a LOW WE. 3. tWR is measured from the earlier of either CS1 or WE going HIGH or CS2 going LOW to the end of the write cycle. 4. During this period, I/O pins are in the output state, and input signals must not be applied. 5. If the CS1 LOW transition or CS2 HIGH transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state. 6. Transition is measured 200mV from steady state. 7. OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is as short as the specified tWP.
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IDT71T024 LOW POWER 2V CMOS STATIC RAM 1 MEG (128K x 8-BIT)
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT 71T024 Device Type L Power XXX Speed XX Package X Process/ Temperature Range Blank I Commercial (0C to +70C) Industrial (-40C to +85C)
PZ
8mm x 13.4mm TSOP Type I
150 200
Speed in nanoseconds
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